(1) Field of the Invention
This invention relates to a memory test circuit and, in particular to the memory test circuit to inspect simply and quickly whether or not the memory devices operate correctly.
(2) Description of the Prior Art
In the past few years, the degree of integration of semiconductor integrated circuit devices, particularly semiconductor memory devices, has increased at a spectacular pace. However, when there is an increase in the number of memory cells on one chip, i.e., in the amount of information recorded, inspecting whether or not these memory cells are functioning correctly becomes correspondingly more difficult, and requires a vast amount of time. This tendency is especially large on a single-bit memory. Because of this, a method of simplifying the testing, reducing testing time (1/4, 1/8) by inspecting a single-bit memory 4 or 8 bits at a time as if it were multi-bit (x4, x8, etc), is coming into use. This method is introduced in, for example, `ISSCC 85 Technical Digest p. 240 "A 90 ns 1 Mb DRAM with Multi-Bit Test Mode"`.
And when there is a increase in the number of memory chips to be inspected simultaneously, in proportion as amount of information recorded on the chip are large, the inspection becomes corresponding more difficult and requires a vast of time.
In existing test simplification methods, however, the testing time is reduced mainly during chip quality selection while still at the wafer stage by setting up additional test output terminals (pads) on the chip, and inspecting multi-bit memory cell by reading the written data from these output terminals. For this reason, this method has the disadvantage of not being applicable to the individual finished products after assembly.
The method of testing by simultaneously reading written data from 4 memory cells and taking the logical product is proposed in the article mentioned above. However, this type of method has the disadvantage that complete inspection cannot be carried out. This is because, although when the data written is "1", then if all the cells are correct, the logical product will be "1" and if only one of the memory cells is faulty, the logical product will be "0", allowing faults to be detected, on the other hand, when the data written is "0", if the output from only one of the memory cells is "0", then the logical product will be "0", giving a "non-faulty" decision.